Filippo Carloni

I am a Postdoctoral Researcher at the National Inter-University Consortium for Telecommunications (CNIT). I am part of the Networks and Systems group of the Advanced Network Technologies Laboratory (ANTLab) at Politecnico di Milano, under the supervision of Prof. Gianni Antichi.

My research sits at the intersection of compilers, network systems, and hardware acceleration. I am interested in programming abstractions and compilers that let developers express what a network application should do, while the system decides where and how to run it efficiently across heterogeneous network infrastructure, from software to programmable hardware. As part of the EU FLECON-6G project, I apply these ideas to offloading network application logic and security functions in next-generation networks.

I started my Ph.D. in Information Technology at Politecnico di Milano in November 2021 and received it in February 2025, with a thesis on Exploiting Hardware and Software Specialization for Efficient Regular Expressions Processing, which won the IEEE Computer Society Italy Chapter PhD Thesis Award (2025 edition). My Ph.D. work co-designed compilers and domain-specific architectures: an MLIR-based compilation flow (CGO 2025), automata-level optimizations for multi-pattern matching (CGO 2024), and the ALVEARE compiler/architecture framework (DAC 2024). During my Ph.D., I was a visiting student at MIT in the COMMIT compiler group led by Prof. Saman Amarasinghe, where I built low-latency, high-throughput SmartNIC processing logic for custom protocols generated by the NetBlocks framework.

The DAC 2024 paper ALVEARE received the HiPEAC Paper Award, and I was a Ph.D. Rocca Project Fellow (2024). I am actively involved in professional service: I regularly serve on artifact evaluation committees for top systems, architecture, and compiler venues (ASPLOS, EuroSys, PLDI, HPCA, CGO, PPoPP, MICRO), on program committees, and as a reviewer for IEEE and ACM journals, and I received the Distinguished Artifact Evaluator Award at EuroSys 2026.

Since 2022, I have been a Teaching Assistant for Computer Architecture and Operating Systems at Politecnico di Milano, a core course of the B.Sc. in Computer Engineering that goes from RISC-V assembly and processor microarchitecture to concurrent programming and operating system internals.

Outside the lab, I am a beekeeper and a truffle hunter: two hobbies that, much like systems research, reward patience and careful observation.

The full list of publications is on the publications page and on Google Scholar.